The ongoing advances in the field of fabricating miniaturized electronic integrated circuits (ICs) has involved the fabrication of multiple layers of interconnects. Interconnects refer to the layer of separate electrical conductors which are formed on top of the substrate and which connect various functional components of the substrate and other electrical connections to the IC. Electrical connections between the interconnect layers and the functional components on the substrate are achieved by “via interconnects,” which are post-like or plug-like vertical connections between the conductors of the interconnect layers and the substrate. Presently manufactured ICs often have five or more interconnect layers formed on top of the substrate.
Only a relatively short time ago, it was impossible or very difficult to construct an IC with more than one or two layers of interconnects. The topology variations created by forming multiple layers on top of one another resulted in such significant depth of focus problems with lithographic processes that any further additions of layers were nearly impossible to achieve. However, recent advances in semiconductor fabrication planarization techniques, such as chemical mechanical polishing (CMP), have been successful in smoothing relatively significant variations in the height or topography of each interconnect layer. As a result of the smoothing, or planarization, conventional lithographic processes are repetitively employed without significant limitation to form considerably more layers of interconnects than had previously been possible.
The multiple interconnect layers consume volume within the IC, although they do not necessarily consume additional substrate surface area. Nevertheless, because surface area and volume are critical considerations in ICs, attention has been focused upon the effective use of the space between the interconnect layers. Normally the space between the interconnect layers is occupied by an insulating material, known as an interlayer dielectric (ILD) or intermetal dielectric (IMD), to insulate the electrical signals conducted by the various conductors of the interconnect layers from each other and from the functional components in the underlying substrate.
One effective use for the space between the interconnect layers is to incorporate capacitors between the interconnect layers in the IMD insulating material separating the interconnect layers. These capacitors form part of the functional components of the IC. Previously, capacitors were constructed in the first layers of IC fabrication immediately above the substrate alongside other structures, such as transistors, so the capacitors were formed of generally the same material used to construct the other functional components, such as polysilicon. Capacitors formed of these materials are generally known as poly-plate capacitors. The aforementioned inventions described in the referenced U.S. patent applications focus on different techniques for combining capacitors with the conductors of the interconnect layers to achieve desirable functional effects within the IC.
Because the conductors of the interconnect layers are metal in construction, the capacitors formed between the interconnect layers are preferably of a metal-insulator-metal (MIM) construction to take advantage of processing steps and performance enhancements. A MIM capacitor has metal plates, usually formed on the metal conductors of the interconnect layers. Because metal fabrication is required for the conductors of the interconnect layers, the simultaneous or near-simultaneous formation of the metal capacitor plates is readily accomplished without significant additional process steps and manufacturing costs. The fifth above identified invention describes a technique for the simultaneous formation of one of the metal capacitor plates integrated with the conductors of the interconnect layers. Thus, at least part of the capacitor is readily fabricated without significant additional process steps and manufacturing costs.
Forming other parts of the capacitor between the interconnects does, however, require additional process steps. The additional process steps involve forming the components of the capacitor in the IMD insulating material and connecting the capacitor components to the conductors of the interconnect layers. In comparison, if the capacitor was not formed in the interlayer insulating material, the entire IMD layer could be conventionally formed. Furthermore, for this method, the via interconnects between the interconnect layers would all have approximately the same depth or height dimension, thereby facilitating the construction of the via interconnects through the IMD insulating material and the formation of the interconnects within the vias. With the presence of the capacitor in the IMD layer, however, the via interconnects do not all have the same depth because the top of the capacitor is higher than the top of the interconnect layer, upon which the capacitor sits. For this case, the selectivity of the IMD material has to be sufficiently high relative to the top electrode material, or the top electrode has to be sufficiently thick, to prevent the via etch process from etching through the top electrode and shorting out the capacitor. In addition, the orientation of the capacitor between the interconnects increases the thickness of the IMD insulating material between the interconnect layers and presents a bulge in the IMD insulating material deposited on top of the capacitor, thereby requiring additional effort, time and/or processing steps in performing the planarization steps to achieve a sufficiently planar surface for the formation of the next vertically-spaced interconnect layer. The increased thickness of the IMD insulating material also consumes additional insulating material, prolongs the fabrication process and increases the variation in IMD thickness, resulting in degraded performance of the IC and/or an increase in defectivity of the ICs thus manufactured. Furthermore, an increased thickness of the IMD increases the overall volume of the IC. In addition to the greater complexity in IC fabrication processing, further design rules must be added to equalize the pattern density of the interconnect layer to prevent formation of topography that cannot be planarized in a conventional CMP process.
It is with respect to these and other background considerations that the present invention has evolved.